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Results 1 to 25 of 7137

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Silicon-on-Nothing MOSFETs : An efficient solution for parasitic substrate coupling suppression in SOI devicesKILCHYTSKA, V; FLANDRE, D; RASKIN, J.-P et al.Applied surface science. 2008, Vol 254, Num 19, pp 6168-6173, issn 0169-4332, 6 p.Conference Paper

Extraction method for substrate resistance of RF MOSFETsHAN, Jeonghu; JE, Minkyu; SHIN, Hyungcheol et al.2002 international conference on microelectronic test structures. 2002, pp 37-40, isbn 0-7803-7464-9, 4 p.Conference Paper

Multiport Thru Deembedding for MOSFET CharacterizationBRINKHOFF, James; ISSAOUN, Ammar; RUSTAGI, Subhash C et al.IEEE electron device letters. 2008, Vol 29, Num 8, pp 923-926, issn 0741-3106, 4 p.Article

A new vertical MOSFET Vertical Logic Circuit (VLC) MOSFET suppressing asymmetric characteristics and realizing an ultra compact and robust logic circuitSAKUI, Koji; ENDOH, Tetsuo.Solid-state electronics. 2010, Vol 54, Num 11, pp 1457-1462, issn 0038-1101, 6 p.Article

A novel surface passivation process for HfO2 Ge MOSFETsNAN WU; QINGCHUN ZHANG; CHUNXIANG ZHU et al.DRC : Device research conference. 2004, pp 19-20, isbn 0-7803-8284-6, 1Vol, 2 p.Conference Paper

A study of source/drain-on-insulator structure for extremely scaled MOSFETsZHIKUAN ZHANG; SHENGDONG ZHANG; CHUGUANG FENG et al.DRC : Device research conference. 2004, pp 115-116, isbn 0-7803-8284-6, 1Vol, 2 p.Conference Paper

Low field mobility characteristics of sub-100 nm unstrained and strained Si MOSFETsRIM, K; NARASIMHA, S; LONGSTREET, M et al.IEDm : international electron devices meeting. 2002, pp 43-46, isbn 0-7803-7462-2, 4 p.Conference Paper

Interface control of high-κ gate dielectrics on GeCAYMAX, M; HOUSSA, M; POURTOIS, G et al.Applied surface science. 2008, Vol 254, Num 19, pp 6094-6099, issn 0169-4332, 6 p.Conference Paper

Validation of MOSFET model source-drain symmetryMCANDREW, Colin C.I.E.E.E. transactions on electron devices. 2006, Vol 53, Num 9, pp 2202-2206, issn 0018-9383, 5 p.Article

A design oriented charge-based current model for symmetric DG MOSFET and its correlation with the EKV formalismSALLESE, Jean-Michel; KRUMMENACHER, Francois; PREGALDINY, Fabien et al.Solid-state electronics. 2005, Vol 49, Num 3, pp 485-489, issn 0038-1101, 5 p.Article

Reduced self-heating by strained silicon substrate engineeringO'NEILL, A; AGAIBY, R; VERHEYEN, P et al.Applied surface science. 2008, Vol 254, Num 19, pp 6182-6185, issn 0169-4332, 4 p.Conference Paper

Gate-extension overlap control by sb tilt implantation : Fundamentals and applications of advanced semiconductor devicesSHIBAHARA, Kentaro; MAEDA, Nobuhide.IEICE transactions on electronics. 2007, Vol 90, Num 5, pp 973-977, issn 0916-8524, 5 p.Article

Mobility enhancement in strained Si NMOSFETs with HfO2 gate dielectricsRIM, K; GUSEV, E. P; LEE, B. H et al.Symposium on VLSI technology. 2002, pp 12-13, isbn 0-7803-7312-X, 2 p.Conference Paper

Low workfunction fully silicided gate on SiO2/Si and LaAlO3/GOI n-MOSFETsYU, D. S; CHIN, Albert; HUNG, B. F et al.DRC : Device research conference. 2004, pp 21-22, isbn 0-7803-8284-6, 1Vol, 2 p.Conference Paper

A Compact Space and Efficient Drain Current Design for Multipillar Vertical MOSFETsSAKUI, Koji; ENDOH, Tetsuo.I.E.E.E. transactions on electron devices. 2010, Vol 57, Num 8, pp 1768-1773, issn 0018-9383, 6 p.Article

Investigating the effects of the interface defects on the gate leakage current in MOSFETsMAO, Ling-Feng.Applied surface science. 2008, Vol 254, Num 20, pp 6628-6632, issn 0169-4332, 5 p.Article

On the parasitic gate capacitance of small-geometry MOSFETsJAGADESH KUMAR, M; VENKATARAMAN, Vivek; SUMEET KUMAR GUPTA et al.I.E.E.E. transactions on electron devices. 2005, Vol 52, Num 7, pp 1676-1677, issn 0018-9383, 2 p.Article

Modeling the effect of source/drain junction depth on bulk-MOSFET scalingMURALI, Raghunath; MEINDL, James D.Solid-state electronics. 2007, Vol 51, Num 6, pp 823-827, issn 0038-1101, 5 p.Article

Exploring the effect of width on performance enhancement in NMOSFETs with a silicon-carbon alloy stressor and a tensile stress silicon nitride linerSHU TONG CHANG; WANG, Wei-Ching; HUANG, Jacky et al.Applied surface science. 2008, Vol 254, Num 19, pp 6177-6181, issn 0169-4332, 5 p.Conference Paper

Fabrication of Ge-channel MOSFETs by using replacement gate process and selective epitaxial growthTERASHIMA, Koichi; TANABE, Akihito; NAKAGAWA, Takashi et al.Applied surface science. 2008, Vol 254, Num 19, pp 6165-6167, issn 0169-4332, 3 p.Conference Paper

Source/drain engineering for MOSFETs with embedded-Si:C technologyITOKAWA, Hiroshi; YASUTAKE, Nobuaki; KUSUNOKI, Naoki et al.Applied surface science. 2008, Vol 254, Num 19, pp 6135-6139, issn 0169-4332, 5 p.Conference Paper

A compact and accurate MOSFET model with simple expressions for linear, saturation and sub-threshold regionsKATTO, Hisao.Solid-state electronics. 2006, Vol 50, Num 3, pp 301-308, issn 0038-1101, 8 p.Article

Extraction of π-type substrate resistance based on three-port measurement and the model verification up to 110 GHzIN MAN KANG; JONG DUK LEE; SHIN, Hyungcheol et al.IEEE electron device letters. 2007, Vol 28, Num 5, pp 425-427, issn 0741-3106, 3 p.Article

Comments on: Modeling MOSFET surface capacitance behavior under non-equilibriumJIN HE; XING ZHANG; YANGYUAN WANG et al.Solid-state electronics. 2006, Vol 50, Num 2, pp 259-262, issn 0038-1101, 4 p.Article

Effect of Device Layout on the Stability of RF MOSFETsYONGHO OH; RIEH, Jae-Sung.IEEE transactions on microwave theory and techniques. 2013, Vol 61, Num 5, pp 1861-1869, issn 0018-9480, 9 p., 1Article

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